An assembled power semiconductor module is shown in FIGS. 10 and 11, where reference numeral 1 denotes a metal base (for example, a copper plate) for heat dissipation, numeral 2 denotes an insulating substrate mounted on the metal base 1, and numeral 3 denotes a heat developing chip component such as a power semiconductor element (hereinafter referred to as “a silicon chip”), which is mounted on an upper surface of the insulating substrate 2. The metal base 1 can be a plate-like metal or a metal provided with a heat radiation fin. When the plate-like metal is used, the heat radiation fin can be joined thereto.
The power semiconductor element is referred to as an IGBT or FWD (Free Wheeling Diode). Reference numeral 4 denotes an external terminal for a main circuit formed in the above power semiconductor element and associated components, numeral 5 denotes a bonding wire, numeral 6 denotes an outer resin case, numeral 7 denotes a top cover, numeral 8 denotes a sealing resin and numeral 9 denotes a gel filler.
Here, the insulating substrate 2 has a structure in which conductor patterns 11 and 12 of copper or aluminum foils are bonded onto both the top and bottom surfaces of the square ceramic substrate 10, respectively. The bonding is carried out by a direct bonding method or an active metal bonding method. With the conductor pattern 11 on the top surface side of the insulating substrate 2 taken as a circuit pattern, the silicon chip 3 is mounted onto the conductor pattern 11 by soldering. Soldering is also provided between the conductor pattern 12 on the bottom surface side of the insulating substrate 2 and the metal base 1. This way, thermal junctions are provided between the silicon chip 3 and the metal base 1. Reference numeral 13 denotes a solder layer of each of soldered sections (see, for example, page 1 of JP-A-10-270612).
Moreover, as will be described later, it is known to mount an IGBT on an insulating substrate to prevent or reduce development of crack, which is induced in the soldered section due to thermal stress applied thereto (see, for example, paragraph 0029 and FIG. 3 of JP-A-2002-76256).
The above-described power semiconductor module needs to reliably operate for a long-term with severity of a service environment and change in an operating temperature. However, a principal part of the above-described power semiconductor module is provided as a layered structure in which component materials each having a different coefficient of thermal expansion are soldered to one another. This causes a severe thermal stress to be applied to each of soldered sections due to a temperature cycle attributed to the service environment of the power semiconductor module and heat developed in the silicon chip 3 associated with an actual operation of the module. In this case, solder is liable to be affected by thermal stress because the melting point thereof is below 300° C. or less, compared with those of other component materials, such as the insulating substrate 2. Therefore, the fatigue life of the soldered section largely affects the reliability and the life of the entire power semiconductor module.
Namely, as presented in FIG. 12, in a solder layer providing a junction between a material A to be joined (coefficient of thermal expansion αA) and a material B to be joined (coefficient of thermal expansion αB), thermal stress is created by the difference in the coefficient of thermal expansion between the materials A and B to be joined, which causes shear strain. The shear strain reaching a region of plastic deformation causes the solder to be subjected to plastic deformation. This is repeated by the temperature cycle to develop solder cracks C over time. The developed solder cracks C further propagates gradually. In this case, in the structure of the module assembled as shown in FIG. 11, the insulating substrate 2 soldered to the metal base 1 square. Therefore, thermal stress, applied to soldered section due to a temperature cycle, concentrates at each of four corners of the insulating substrate 2, where an amount of thermal expansion or contraction becomes maximum as shown in FIG. 13. This causes in the soldered section the solder crack C to develop with each of the four corners of the insulating substrate 2 as a starting point. The solder crack C gradually grows toward the center of the insulating substrate 2 from each of the four corners with repetition of the temperature cycle.
Moreover, when the solder crack C, developed at the corner of the insulating substrate 2, grows to a joint face region with the silicon chip 3 (see FIG. 11) mounted on the substrate, the solder cracks C prevent heat transfer from the insulating substrate 2 to the metal base 1 for proper heat dissipation. This interrupts heat dissipation from the silicon chip 3, raising the junction temperature of the semiconductor element, which will lead to possible thermal breakdown.
Moreover, in a semiconductor device assembled by adopting the insulating substrate 2 made of ceramic, there is a larger difference in coefficient of thermal expansion between the insulating substrate 2 and the metal base 1 compared with the difference in coefficient of thermal expansion between the silicon chip 3 and the insulating substrate 2. In addition, the soldered section between the insulating substrate 2 and the metal base 1 has a larger joint area compared with that of the soldered section between the insulating substrate 2 and the silicon chip 3. This increases the amount of strain induced at the soldered section between the insulating substrate 2 and the metal base 1 due to repetition of the temperature cycle. Therefore, the solder cracks C in the soldered section develops in a shorter period while increasing the propagating period of the solder cracks C. The above JP-A-2002-76256 discloses suppressing cracks induced in the soldered section.
In this regard, in a semiconductor module using a substrate of ceramic such as aluminum nitride, the metal base 1 has been made of a material with a lower coefficient of thermal expansion than that of copper (coefficient of thermal expansion of 16.5 ppm/K) to lessen the difference in coefficient of thermal expansion between the insulating substrate 2 and the metal base 1 for the purpose of relaxing thermal stress applied to the soldered section. Specifically, a composite material of aluminum and silicon carbide (coefficient of thermal expansion of 7 ppm/K), a composite material of copper and molybdenum (coefficient of thermal expansion of 7 to 8 ppm/K), or molybdenum (coefficient of thermal expansion of 5 ppm/K), has been used to form the metal base 1.
The above materials with low thermal expansion, however, have about 50% less thermal conductivity (thermal conductivity of 398 W/mK, as opposed to 180 to 210 W/mK). Thus, the materials have inferior heat dissipation performance as substrates. Furthermore, these materials with low thermal expansion, being manufactured by using such a special method as to sinter or impregnate SiC or Mo having a high melting point and being hard to be machined, are expensive compared with copper material. This increases the cost of the semiconductor module.
Moreover, as another solution for lessening the stress applied to the soldered section, the thickness of the solder layer between the insulating substrate 2 and the metal base 1 is increased to lessen thermal stress created in the soldered section. Although this method is effective for extending the life of the soldered section, however, the thermal resistance at the joined section increases with the increasing thickness, lowering the heat dissipation. Furthermore, increasing the thickness of the soldered section increases the amount of solder being used to produce solder balls or cause a solder overflow in a module assembling process (a soldering process), lowering the product yield. Further, it is technically difficult to uniformly maintain the thickness of the solder layer.
Accordingly, there still remains a need to improve the life of a semiconductor device by suppressing the development of solder crack. The present invention addresses this need.